Syndetics cover image
Image from Syndetics

The Designer's Guide to the Cortex-M Processor Family.

By: Material type: TextPublisher: Chantilly : Elsevier Science & Technology, 2016Copyright date: ©2016Edition: 2nd edDescription: 1 online resource (492 pages)Content type:
  • text
Media type:
  • computer
Carrier type:
  • online resource
ISBN:
  • 9780081006344
Subject(s): Genre/Form: DDC classification:
  • 004.16
Online resources:
Contents:
Front Cover -- {u0093}{u0093}{u0093}The Designer's Guide to the Cortex-M Processor Family{u0093}{u0093}{u0093}{u0093}{u0093} -- Copyright Page -- Dedication -- Contents -- Foreword -- Preface -- Acknowledgments -- 1 Introduction to the Cortex-M Processor Family -- Cortex Profiles -- Cortex-M3 -- Advanced Architectural Features -- Cortex-M0 -- Cortex-M0+ -- Cortex-M4 -- DSP Instructions -- Cortex-M7 -- Conclusion -- 2 Developing Software for the Cortex-M Family -- Introduction -- Keil Microcontroller Development Kit -- Software Packs -- The Tutorial Exercises -- Installation -- Exercise 2.1 Building a First Program -- The Blinky Project -- Project Configuration -- Exercise 2.2 Hardware Debug -- Conclusion -- 3 Cortex-M Architecture -- Introduction -- Cortex-M Instruction Set -- Programmer's Model and CPU Registers -- Program Status Register -- Q Bit and Saturated Maths Instructions -- Interrupts and Multicycle Instructions -- Conditional Execution-If Then Blocks -- Exercise 3.1 Saturated Maths and Conditional Execution -- Cortex-M Memory Map and Busses -- Write Buffer -- Memory Barrier Instructions -- System Control Block -- Bit Manipulation -- Exercise 3.2 Bit Banding -- Dedicated Bit Manipulation Instructions -- SysTick Timer -- Nested Vector Interrupt Controller -- Operating Modes -- Interrupt Handling-Entry -- Interrupt Handling-Exit -- Interrupt Handling-Exit Important! -- Exercise 3.3 SysTick Interrupt -- Cortex-M Processor Exceptions -- Usage Fault -- Bus Fault -- Memory Manager Fault -- Hard Fault -- Enabling Fault Exceptions -- Priority and Preemption -- Groups and Subgroup -- Runtime Priority Control -- Exception Model -- NVIC Tail Chaining -- NVIC Late Arriving -- NVIC POP Preemption -- Exercise 3.3 Working with Multiple Interrupts -- Bootloader Support -- Exercise 3.4 Bootloader -- Power Management -- Entering Low-Power Modes -- Configuring the Low-Power Modes.
Exercise 3.3 Low-Power Modes -- Moving From the Cortex-M3 -- Cortex-M4 -- Cortex-M0 -- Cortex-M0+ -- Conclusion -- 4 Cortex Microcontroller Software Interface Standard -- Introduction -- CMSIS Specifications -- CMSIS-Core -- CMSIS-RTOS -- CMSIS-DSP -- CMSIS-Driver -- CMSIS-SVD and DAP -- CMSIS-Pack -- Foundations of CMSIS -- Coding Rules -- MISRA-C -- CMSIS-Core Structure -- Startup Code -- System Code -- Device Header File -- CMSIS-Core Header Files -- Interrupts and Exceptions -- Exercise 4.1 CMSIS and User Code Comparison -- CMSIS-Core Register Access -- CMSIS-Core CPU Intrinsic Instructions -- Exercise 4.2 Intrinsic Bit Manipulation -- CMSIS-SIMD Intrinsics -- CMSIS-Core Debug Functions -- Hardware Breakpoint -- Instrumentation Trace -- CMSIS-Core Functions for Corex-M7 -- Conclusion -- 5 Advanced Architecture Features -- Introduction -- Cortex Processor Operating Modes -- Exercise 5.1 Stack Configuration -- Supervisor Call -- Exercise 5.2 Supervisor Call -- PEND_SV Exception -- Example Pend_SV -- Interprocessor Events -- Exclusive Access -- Exercise 5.4 Exclusive Access -- Memory Protection Unit -- Configuring the MPU -- Exercise 5.5 MPU Configuration -- MPU Subregions -- MPU Limitations -- AHB Lite Bus Interface -- Conclusion -- 6 Cortex-M7 Processor -- Superscalar Architecture -- Branch Prediction -- Exercise 6.1 Simple Loop -- Bus Structure -- Memory Hierarchy -- Exercise 6.2 Locating Code and Data into the TCM -- Cache Units -- Cache Operation -- Instruction Cache -- Exercise 6.3 Instruction Cache -- Data Cache -- Memory Barriers -- Exercise 6.4 Example Data Cache -- Memory Protection Unit and Cache Configuration -- Cache Policy -- Managing the Data Cache -- Switch Off the Cache -- Disable Caching over a Region of System Memory -- Change the Cache Policy for a Region of System Memory.
Use the Cache Management Functions to Guarantee Coherency -- Exercise 6.5 Data Cache Configuration -- Double Precision Floating Point Unit -- Functional Safety -- Cortex-M7 Safety Features -- Safety Documentation -- Development Tools -- Conclusion -- 7 Debugging with CoreSight -- Introduction -- CoreSight Hardware -- Debugger Hardware -- CoreSight Debug Architecture -- Exercise 7.1 CoreSight Debug -- Hardware Configuration -- Software Configuration -- Debug Limitations -- Instrumentation Trace -- Exercise 7.2 Setting Up the ITM -- System Control Block Debug Support -- Tracking Faults -- Exercise 7.3 Processor Fault Exceptions -- Instruction Trace with the Embedded Trace Macrocell -- Exercise 7.4 Using the ETM Trace -- CMSIS-DAP -- Cortex-M0+ MTB -- Exercise 7.5 Micro Trace Buffer -- CMSIS System Viewer Description -- Exercise 7.6 CMSIS-SVD -- Conclusion Debug Features Summary -- 8 Practical DSP for Cortex-M4 and Cortex-M7 -- Introduction -- Hardware FPU -- FPU Integration -- FPU Registers -- Cortex-M7 FPU -- Enabling the FPU -- Exceptions and the FPU -- Using the FPU -- Exercise 8.1 Floating Point Unit -- Cortex-M4/M7 DSP and SIMD Instructions -- Exercise 8.2 SIMD Instructions -- Exercise 8.3 Optimizing DSP Algorithms -- The CMSIS-DSP Library -- CMSIS-DSP Library Functions -- Exercise 8.3 Using the CMSIS-DSP Library -- DSP Data Processing Techniques -- Exercise 8.4 FIR Filter with Block Processing -- Fixed Point DSP with Q Numbers -- Exercise 8.5 Fixed Point FFT Transform -- Conclusion -- 9 Cortex Microcontroller Software Interface Standard-Real-Time Operating System -- Introduction -- First Steps with CMSIS-RTOS -- Accessing the CMSIS-RTOS API -- Threads -- Starting the RTOS -- Exercise 9.1 A First CMSIS-RTOS Project -- Creating Threads -- Exercise 9.2 Creating and Managing Threads -- Thread Management and Priority.
Exercise 9.3 Creating and Managing Threads II -- Multiple Instances -- Exercise 9.4 Multiple Thread Instances -- Time Management -- Time Delay -- Waiting for an Event -- Exercise 9.5 Time Management -- Virtual Timers -- Exercise 9.6 Virtual Timer -- Sub-Millisecond Delays -- Idle Demon -- Exercise 9.7 Idle Thread -- Inter-Thread Communication -- Signals -- Exercise 9.8 Signals -- Semaphores -- Exercise 9.9 Semaphore Signaling -- Using Semaphores -- Signaling -- Multiplex -- Exercise 9.10 Multiplex -- Rendezvous -- Exercise 9.11 Rendezvous -- Barrier Turnstile -- Exercise 9.12 Semaphore Barrier -- Semaphore Caveats -- Mutex -- Exercise 9.13 Mutex -- Mutex Caveats -- Data Exchange -- Message Queue -- Exercise 9.14 Message Queue -- Memory Pool -- Exercise 9.15 Memory Pool -- Mail Queue -- Exercise 9.16 Mailbox -- Configuration -- Thread Definition -- Kernel Debug Support -- System Timer Configuration -- Timeslice Configuration -- Scheduling Options -- Preemptive Scheduling -- Round-Robin Scheduling -- Round-Robin Preemptive Scheduling -- Cooperative Multitasking -- RTX Source Code -- RTX License -- Conclusion -- 10 RTOS Techniques -- Introduction -- RTOS and Interrupts -- RTOS Interrupt Handling -- Exercise 10.1 RTOS Interrupt Exercise Handling -- User Supervisor Functions -- Exercise 10.2 RTOS and User SVC Exceptions -- Power Management -- Power Management First Steps -- Power Management Strategy -- Watchdog Management -- Integrating ISRs -- Exercise 10.3 Power and Watchdog Management -- Startup Barrier -- Designing for Real Time -- Buffering Techniques-The Double or Circular Buffer -- Buffering Techniques FIFO Message Queue -- Balancing the Load -- Exercise 10.4 RTX Real Time -- Shouldering the Load, the Direct Memory Access Controller -- Designing for Debug -- Exercise 10.5 Run-Time Diagnostics -- Conclusion -- 11 Test Driven Development.
Introduction -- The TDD Development Cycle -- Test Framework -- Test Automation -- Installing the Unity Framework -- Exercise 11.1 Test Driven Development -- Adding the Unity Test Framework -- Configuring the Project Build Targets -- Adding the Test Cases -- Automating the TDD Cycle -- Testing RTOS Threads -- Exercise 11.2 Testing RTOS Threads -- Decoupling Low Level Functions -- Testing Interrupts -- Exercise 11.3 Testing with Interrupts -- Conclusion -- 12 Software Components -- Introduction -- CMSIS Driver -- CMSIS Driver API -- Exercise 12.1 CMSIS-Driver -- Driver Validation -- Exercise 12.2 Driver Validation -- Designing a Software Component -- Exercise 12.3 GPS Component -- Creating a Software Pack -- Software Pack Structure -- Software Pack Utilities -- Configuration Wizard -- Exercise 12.4 Configuration Wizard -- Deploying Software Components -- Conclusion -- 13 ARMv8-M -- Introduction -- Common Architectural Enhancements -- ARMv8 Baseline Enhancements -- ARMv8-M Mainline Enhancements -- TrustZone -- Interrupts and Exceptions -- Software Development -- Compiler -- Real-Time Operating System -- Debugger -- Cortex Microcontroller Software Interface Standard -- Conclusion -- Appendix -- Contact Details -- Appendices -- Debug Tools and Software -- Commercial GNU-Based Toolchains -- Commercial Toolchains -- Rapid Prototyping and Evaluation Modules -- Real-Time Operating Systems -- Digital Signal Processing -- Books -- Programming -- Cortex-M Processor -- Standards -- Digital Signal Processing -- Real-Time Operating System -- Silicon Vendors -- Training -- Index -- Back Cover.
No physical items for this record

Front Cover -- {u0093}{u0093}{u0093}The Designer's Guide to the Cortex-M Processor Family{u0093}{u0093}{u0093}{u0093}{u0093} -- Copyright Page -- Dedication -- Contents -- Foreword -- Preface -- Acknowledgments -- 1 Introduction to the Cortex-M Processor Family -- Cortex Profiles -- Cortex-M3 -- Advanced Architectural Features -- Cortex-M0 -- Cortex-M0+ -- Cortex-M4 -- DSP Instructions -- Cortex-M7 -- Conclusion -- 2 Developing Software for the Cortex-M Family -- Introduction -- Keil Microcontroller Development Kit -- Software Packs -- The Tutorial Exercises -- Installation -- Exercise 2.1 Building a First Program -- The Blinky Project -- Project Configuration -- Exercise 2.2 Hardware Debug -- Conclusion -- 3 Cortex-M Architecture -- Introduction -- Cortex-M Instruction Set -- Programmer's Model and CPU Registers -- Program Status Register -- Q Bit and Saturated Maths Instructions -- Interrupts and Multicycle Instructions -- Conditional Execution-If Then Blocks -- Exercise 3.1 Saturated Maths and Conditional Execution -- Cortex-M Memory Map and Busses -- Write Buffer -- Memory Barrier Instructions -- System Control Block -- Bit Manipulation -- Exercise 3.2 Bit Banding -- Dedicated Bit Manipulation Instructions -- SysTick Timer -- Nested Vector Interrupt Controller -- Operating Modes -- Interrupt Handling-Entry -- Interrupt Handling-Exit -- Interrupt Handling-Exit Important! -- Exercise 3.3 SysTick Interrupt -- Cortex-M Processor Exceptions -- Usage Fault -- Bus Fault -- Memory Manager Fault -- Hard Fault -- Enabling Fault Exceptions -- Priority and Preemption -- Groups and Subgroup -- Runtime Priority Control -- Exception Model -- NVIC Tail Chaining -- NVIC Late Arriving -- NVIC POP Preemption -- Exercise 3.3 Working with Multiple Interrupts -- Bootloader Support -- Exercise 3.4 Bootloader -- Power Management -- Entering Low-Power Modes -- Configuring the Low-Power Modes.

Exercise 3.3 Low-Power Modes -- Moving From the Cortex-M3 -- Cortex-M4 -- Cortex-M0 -- Cortex-M0+ -- Conclusion -- 4 Cortex Microcontroller Software Interface Standard -- Introduction -- CMSIS Specifications -- CMSIS-Core -- CMSIS-RTOS -- CMSIS-DSP -- CMSIS-Driver -- CMSIS-SVD and DAP -- CMSIS-Pack -- Foundations of CMSIS -- Coding Rules -- MISRA-C -- CMSIS-Core Structure -- Startup Code -- System Code -- Device Header File -- CMSIS-Core Header Files -- Interrupts and Exceptions -- Exercise 4.1 CMSIS and User Code Comparison -- CMSIS-Core Register Access -- CMSIS-Core CPU Intrinsic Instructions -- Exercise 4.2 Intrinsic Bit Manipulation -- CMSIS-SIMD Intrinsics -- CMSIS-Core Debug Functions -- Hardware Breakpoint -- Instrumentation Trace -- CMSIS-Core Functions for Corex-M7 -- Conclusion -- 5 Advanced Architecture Features -- Introduction -- Cortex Processor Operating Modes -- Exercise 5.1 Stack Configuration -- Supervisor Call -- Exercise 5.2 Supervisor Call -- PEND_SV Exception -- Example Pend_SV -- Interprocessor Events -- Exclusive Access -- Exercise 5.4 Exclusive Access -- Memory Protection Unit -- Configuring the MPU -- Exercise 5.5 MPU Configuration -- MPU Subregions -- MPU Limitations -- AHB Lite Bus Interface -- Conclusion -- 6 Cortex-M7 Processor -- Superscalar Architecture -- Branch Prediction -- Exercise 6.1 Simple Loop -- Bus Structure -- Memory Hierarchy -- Exercise 6.2 Locating Code and Data into the TCM -- Cache Units -- Cache Operation -- Instruction Cache -- Exercise 6.3 Instruction Cache -- Data Cache -- Memory Barriers -- Exercise 6.4 Example Data Cache -- Memory Protection Unit and Cache Configuration -- Cache Policy -- Managing the Data Cache -- Switch Off the Cache -- Disable Caching over a Region of System Memory -- Change the Cache Policy for a Region of System Memory.

Use the Cache Management Functions to Guarantee Coherency -- Exercise 6.5 Data Cache Configuration -- Double Precision Floating Point Unit -- Functional Safety -- Cortex-M7 Safety Features -- Safety Documentation -- Development Tools -- Conclusion -- 7 Debugging with CoreSight -- Introduction -- CoreSight Hardware -- Debugger Hardware -- CoreSight Debug Architecture -- Exercise 7.1 CoreSight Debug -- Hardware Configuration -- Software Configuration -- Debug Limitations -- Instrumentation Trace -- Exercise 7.2 Setting Up the ITM -- System Control Block Debug Support -- Tracking Faults -- Exercise 7.3 Processor Fault Exceptions -- Instruction Trace with the Embedded Trace Macrocell -- Exercise 7.4 Using the ETM Trace -- CMSIS-DAP -- Cortex-M0+ MTB -- Exercise 7.5 Micro Trace Buffer -- CMSIS System Viewer Description -- Exercise 7.6 CMSIS-SVD -- Conclusion Debug Features Summary -- 8 Practical DSP for Cortex-M4 and Cortex-M7 -- Introduction -- Hardware FPU -- FPU Integration -- FPU Registers -- Cortex-M7 FPU -- Enabling the FPU -- Exceptions and the FPU -- Using the FPU -- Exercise 8.1 Floating Point Unit -- Cortex-M4/M7 DSP and SIMD Instructions -- Exercise 8.2 SIMD Instructions -- Exercise 8.3 Optimizing DSP Algorithms -- The CMSIS-DSP Library -- CMSIS-DSP Library Functions -- Exercise 8.3 Using the CMSIS-DSP Library -- DSP Data Processing Techniques -- Exercise 8.4 FIR Filter with Block Processing -- Fixed Point DSP with Q Numbers -- Exercise 8.5 Fixed Point FFT Transform -- Conclusion -- 9 Cortex Microcontroller Software Interface Standard-Real-Time Operating System -- Introduction -- First Steps with CMSIS-RTOS -- Accessing the CMSIS-RTOS API -- Threads -- Starting the RTOS -- Exercise 9.1 A First CMSIS-RTOS Project -- Creating Threads -- Exercise 9.2 Creating and Managing Threads -- Thread Management and Priority.

Exercise 9.3 Creating and Managing Threads II -- Multiple Instances -- Exercise 9.4 Multiple Thread Instances -- Time Management -- Time Delay -- Waiting for an Event -- Exercise 9.5 Time Management -- Virtual Timers -- Exercise 9.6 Virtual Timer -- Sub-Millisecond Delays -- Idle Demon -- Exercise 9.7 Idle Thread -- Inter-Thread Communication -- Signals -- Exercise 9.8 Signals -- Semaphores -- Exercise 9.9 Semaphore Signaling -- Using Semaphores -- Signaling -- Multiplex -- Exercise 9.10 Multiplex -- Rendezvous -- Exercise 9.11 Rendezvous -- Barrier Turnstile -- Exercise 9.12 Semaphore Barrier -- Semaphore Caveats -- Mutex -- Exercise 9.13 Mutex -- Mutex Caveats -- Data Exchange -- Message Queue -- Exercise 9.14 Message Queue -- Memory Pool -- Exercise 9.15 Memory Pool -- Mail Queue -- Exercise 9.16 Mailbox -- Configuration -- Thread Definition -- Kernel Debug Support -- System Timer Configuration -- Timeslice Configuration -- Scheduling Options -- Preemptive Scheduling -- Round-Robin Scheduling -- Round-Robin Preemptive Scheduling -- Cooperative Multitasking -- RTX Source Code -- RTX License -- Conclusion -- 10 RTOS Techniques -- Introduction -- RTOS and Interrupts -- RTOS Interrupt Handling -- Exercise 10.1 RTOS Interrupt Exercise Handling -- User Supervisor Functions -- Exercise 10.2 RTOS and User SVC Exceptions -- Power Management -- Power Management First Steps -- Power Management Strategy -- Watchdog Management -- Integrating ISRs -- Exercise 10.3 Power and Watchdog Management -- Startup Barrier -- Designing for Real Time -- Buffering Techniques-The Double or Circular Buffer -- Buffering Techniques FIFO Message Queue -- Balancing the Load -- Exercise 10.4 RTX Real Time -- Shouldering the Load, the Direct Memory Access Controller -- Designing for Debug -- Exercise 10.5 Run-Time Diagnostics -- Conclusion -- 11 Test Driven Development.

Introduction -- The TDD Development Cycle -- Test Framework -- Test Automation -- Installing the Unity Framework -- Exercise 11.1 Test Driven Development -- Adding the Unity Test Framework -- Configuring the Project Build Targets -- Adding the Test Cases -- Automating the TDD Cycle -- Testing RTOS Threads -- Exercise 11.2 Testing RTOS Threads -- Decoupling Low Level Functions -- Testing Interrupts -- Exercise 11.3 Testing with Interrupts -- Conclusion -- 12 Software Components -- Introduction -- CMSIS Driver -- CMSIS Driver API -- Exercise 12.1 CMSIS-Driver -- Driver Validation -- Exercise 12.2 Driver Validation -- Designing a Software Component -- Exercise 12.3 GPS Component -- Creating a Software Pack -- Software Pack Structure -- Software Pack Utilities -- Configuration Wizard -- Exercise 12.4 Configuration Wizard -- Deploying Software Components -- Conclusion -- 13 ARMv8-M -- Introduction -- Common Architectural Enhancements -- ARMv8 Baseline Enhancements -- ARMv8-M Mainline Enhancements -- TrustZone -- Interrupts and Exceptions -- Software Development -- Compiler -- Real-Time Operating System -- Debugger -- Cortex Microcontroller Software Interface Standard -- Conclusion -- Appendix -- Contact Details -- Appendices -- Debug Tools and Software -- Commercial GNU-Based Toolchains -- Commercial Toolchains -- Rapid Prototyping and Evaluation Modules -- Real-Time Operating Systems -- Digital Signal Processing -- Books -- Programming -- Cortex-M Processor -- Standards -- Digital Signal Processing -- Real-Time Operating System -- Silicon Vendors -- Training -- Index -- Back Cover.

Description based on publisher supplied metadata and other sources.

Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2025. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.

Licensed e-book