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Thread and Data Mapping for Multicore Systems [electronic resource] : Improving Communication and Memory Accesses / by Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux.

By: Contributor(s): Material type: TextSeries: SpringerBriefs in Computer SciencePublisher: Cham : Springer International Publishing : Imprint: Springer, 2018Edition: 1st ed. 2018Description: 1 online resource (IX, 54 p. 34 illus.)Content type:
  • text
Media type:
  • computer
Carrier type:
  • online resource
ISBN:
  • 9783319910741
Subject(s): Additional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification:
  • 004 23
LOC classification:
  • TK7885-7895
Online resources:
Contents:
preface -- chapter 1: introduction -- chapter 2: Sharing-aware mapping and parallel architectures -- chapter 3: Sharing-aware mapping and parallel applications -- chapter 4: Sharing-Aware mapping methods -- chapter 5: Improving performance with Sharing-Aware mapping -- chapter 6: conclusion and research prospects -- index.
In: Springer Nature eBookSummary: This book presents a study on how thread and data mapping techniques can be used to improve the performance of multi-core architectures. It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures. On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access. Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.
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preface -- chapter 1: introduction -- chapter 2: Sharing-aware mapping and parallel architectures -- chapter 3: Sharing-aware mapping and parallel applications -- chapter 4: Sharing-Aware mapping methods -- chapter 5: Improving performance with Sharing-Aware mapping -- chapter 6: conclusion and research prospects -- index.

This book presents a study on how thread and data mapping techniques can be used to improve the performance of multi-core architectures. It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures. On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access. Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.

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